It further exports Context Word broadcast functions for row-, column-, and array broadcast. The array component simply provides functions to set data input for each RC instance and to access output data from them. This component assembles an 8x8 MorphoSys RC Array by instantiating the MorphoSys RC COM component. AsmL COM integration was used to make the RC component available to the MorphoSys RC Array component described in the next paragraph.

Thus, AsmL again proved to be an efficient way to define languages as well as to parse, accept, and translate them. This ASM was also extended with assembler capabilities in order to produce an output language L out with an output word w el.of L out (binary or hex values) for each legal input Context Word. Abstract State Machines define automats M that accept the BNF defined Context Words w el.of L in that present the input language L in. MorphoSys Context Words were given in Backus-Naur forms. Part of the MorphoSys RC component is an AsmL class that represents an Abstract State Machine to accept a defined SIMD assembly language instruction set. One simply has to model a behavior representing Abstract State Machine for that new instruction and to add required global attributes. The given example of such a behavior oriented approach makes clear that it is very easy to modify the specification of an existing opcode or to add the behavior of new instructions that may even employ further computer architecture attributes. According to the ASM computation model, each call of an instruction function changes the interpretation of subsequent instruction functions. Thus, every instruction defines sub states within the MorphoSys RC Abstract State Machine. The top-level hierarchy of the MorphoSys RC behavior as well as every instruction is modeled as an Abstract State Machine. 9 shows the AsmL source code for the read predicated ADD instruction. An example for such a “virtual” attribute is the clockCycles variable. Not all of these variables have their equivalent counterpart in hardware but are essential for a complete specification. These variables define external data input, visible data registers, and ALU flag generation- and predication related attributes. Every RC instruction is represented by an Abstract State Machine that operates on global variables given in Fig.

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